When the technology for manufacturing the MOS devices is gradually progressing into the deep sub-micron era, some problems which are not essential in the sub-micron process now become very important. For example, the conventional source/drain extension process meets a problem in the coincidence of lightly doped drain (LDD) and source/drain extension junctions underneath gate edge of a MOSFET. The coincidence of these junctions induces large reverse junction current that forces device become leakage. Furthermore, a high impact ionization rate will worsen the hot carrier effect. A discussion about the related problems can be found in Lisa T. Su (1996).
A conventional method for manufacturing a MOSFET is illustrated in FIGS. 1(a) to 1(e). Referring to FIG. 1(a), when the MOS structure including the gate oxide 13 and the gate 14 on a substrate 10 has been made, an ion implantation is executed to form the lightly doped areas 16 of the source and drain. This step is so called a "lightly doped drain" (LDD) process. To decrease the resistance of the lightly doped areas 16, another ion implantation is executed to form enhanced lightly doped areas 11 having a penetration depth shallower than that of the lightly doped areas 16 of the source and drain. Then a dielectric layer 15 is deposited over the gate 14 and the gate oxide 13. The dielectric layer 15 is etched to form the spacer 15a. After then, a heavily doped process is executed to form the heavily doped areas 12 to form the major portion of the source 17 and drain 18 of the MOS transistor 1. However, since the ion implantations of the lightly doped areas 16 and the enhanced lightly doped areas 11 use the same mask, i.e., the gate 14, most part of the junctions of the lightly doped areas 16 and the gate oxide 13 will overlap with the junctions between the enhanced lightly doped areas 11 and the gate oxide 13. The extensions of the source/drain are formed by portions 16a of the enhanced lightly doped areas 16 which are extended from the heavily doped areas 12. In the conventional process, the formation of the extensions 16a of the source/drain cannot be properly controlled, so the extension junctions of the source/drain are located too close to the channel of the transistor, which will decrease the performance of the MOSFET with LDD structure. The defects of the conventional process can be summarized as follows:
1. The coincidence of the junctions of the lightly doped source/drain and the extensions of the source/drain will cause a large reverse junction current and thus induce a current leakage of the transistor. PA0 2. Such a structure will increase the probability of ion collisions so that the hot carrier effect will be aggravated.
To solve the above-mentioned problems, the present invention provides a method for manufacturing a MOSFET with adjustable source/drain extensions.